Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
PEST: a tool for implementing pseudo-exhaustive self test
EURO-DAC '90 Proceedings of the conference on European design automation
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
An Algorithm for the Generation of Test Sets for Combinational Logic Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new pseudo-exhaustive testing algorithm that is composed of the path sensitization and sub-circuit partitioning using t-distribution. In the proposed testing algorithm, the paths, for the path sensitization the, between PIs and POs based on the high TMY(test-mainstay) nodes of CUT(circuit under test) are sensitized and the boundary nodes, for the partitioned sub-circuits, are defined on the level of significance α on t-distribution respectively. As a consequence, when (1-α) is 0.2368, the most suitable of the performance to operate the singular cover and consistency operation in the path sensitization. And when α is 0.5217, the most suitable of the performance to partition the sub-circuit in sub-circuit partitioning.