Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design

Authors:
Chien-In Henry Chen;Joel T. Yuen
Affiliations:
Department of Electrical Engineering, Wright State University, Dayton, OH;Department of Electrical Engineering, Wright State University, Dayton, OH
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 11
Cited 1

Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique

IEEE Transactions on Computers - The MIT Press scientific computation series
MIPS RISC architecture

MIPS RISC architecture
Gentest: An Automatic Test-Generation System for Sequential Circuits

Computer
Differential fault simulation - a fast method using minimal memory

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Combinatorial Algorithms: Theory and Practice

Combinatorial Algorithms: Theory and Practice
Design for Testability A Survey

IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique

IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing

IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms

IEEE Transactions on Computers
Built-In Self-Test Techniques

IEEE Design & Test

Path sensitization and sub-circuit partition of CUT using t,-distribution for pseudo-exhaustive testing

AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named Three-Phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on Three-Phase Cluster Partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented.