Can we eliminate fault escape in self testing by polynomial division (signature analysis)?

Authors:
Dilip K. Bhavsar;Balakrishnan Krishnamurthy
Affiliations:
Digital Equipment Corporation, Hudson, MA;General Electric Research Center, Schenectady, NY
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

Citing 3
Cited 0

Measures of the Effectiveness of Fault Signature Analysis

IEEE Transactions on Computers
Design for Autonomous Test

IEEE Transactions on Computers
Design for Autonomous Test

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper is based on a search for an ideal signature analysis scheme that will ensure that the detected faults do not escape due to error masking. We present a number of general techniques based on linear feedback shift registers and characterize them for their impact on error escape and fault escape. We show that, under certain conditions of uniformity, the error escape probability of any general data compression scheme is governed by a fundamental information theoretic lower bound. We then demonstrate that the techniques suggested in this paper conform to the established lower bound, but elimination or even reduction of fault escape by them cannot be guaranteed.