Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
Analysis of the Signal Reliability Measure and an Evaluation Procedure
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Electrical design of a high speed computer package
IBM Journal of Research and Development
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Linear Dependencies in Linear Feedback Shift Registers
IEEE Transactions on Computers
Bounding Signal Probabilities in Combinational Circuits
IEEE Transactions on Computers
Fault Propagation Through Embedded Multiport Memories
IEEE Transactions on Computers
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IEEE Transactions on Computers
Optimal periodic testing policy for circuit with self-testing
Computers & Mathematics with Applications
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Random testing for stuck-at storage cells in an embedded memory
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
The coverage problem for random testing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.01 |
A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.