High-Level Test Generation Using Symbolic Scheduling

Gate-level test generation for sequential circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

RTL Test Justification and Propagation Analysis for Modular Designs

Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis

Deterministic Built-in Pattern Generation for Sequential Circuits

Journal of Electronic Testing: Theory and Applications

Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering

IEEE Design & Test

19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Reducing Test Application Time in High-Level Test Generation

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Fast Test Generation for Circuits with RTL and Gate-Level Views

ITC '01 Proceedings of the 2001 IEEE International Test Conference