Data structures and network algorithms
Data structures and network algorithms
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A framework for testing core-based systems-on-a-chip
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Introduction to the Theory of Computation
Introduction to the Theory of Computation
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Graph Theory With Applications
Graph Theory With Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Available register-transfer level (RTL) test generation techniquesdo not make a concerted effort to reduce the test application timeassociated with the derived tests. Chip tester memory limitations,increasing tester costs, etc., make it imperative that the issue ofgenerating compact tests at the RTL be addressed and consolidatedwith the known gains of high-level testing. In this paper, weprovide a comprehensive framework for generating compact testsfor an RTL circuit. We develop a series of techniques that exploitthe inherent parallelism available in symbolic test(s) derived forRTL module(s). These techniques enable us to schedule testing ofmultiple modules in parallel as well as perform test pipelining. Inaddition, we also present design for testability (DFT) techniquesfor lowering test application time. Using a maximum bipartitematching formulation, we choose a low-overhead set of test enhancements that can achieve compact tests. Our techniques canseamlessly plug into any generic high-level test framework. Ourexperimental results in the context of one such framework indicatethat the proposedmethodology achieves an average reductionin test application time of 61.1% for the example circuits.