A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introduction to the Theory of Computation
Introduction to the Theory of Computation
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
System chip test: are we there yet?
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Reducing Test Application Time in High-Level Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions. In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs. First, we develop a common ground for addressing issues such as core test requirements, core access and test hardware additions. For this purpose, we introduce finite-state automata for modeling tests, transparency modes and test hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data which can again be modeled using finite-state automata. While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automation, this work extends the methodology to the system level, and, additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. This problem is known to be a bottleneck in testability analysis not only at the system level, but also at the RTL. Experimental results show that the system-level average area overhead for making SOCs testable with our method is only 4.4%, while achieving an average test application time reduction of 78.5% over recent approaches. At the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores.