Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Introduction to the Theory of Computation: Preliminary Edition
Introduction to the Theory of Computation: Preliminary Edition
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a simple two-pass strategy that couplesregister-transfer level (RTL) test generation with gate-levelsequential test generation through fault lists. We motivate thisapproach by showing that faults found hard-to-test by gate-levelsequential test generators are often easily testable at the RTL.Likewise, modules found symbolically untestable at the RTL havemany of their faults testable at the gate level. Therefore, a two-passstrategy, which runs a fast RTL test generator followed bya gate-level sequential test generator on the remaining untestedfaults, can leverage off the strengths of each test generator. Nomodifications are necessary to the source code of either test generatorto make this approach work. This makes it particularly attractiveto industrial test flows, where the available gate-level testgenerator may be from a commercial vendor. This is in contrastto many hierarchical test generation techniques where there is significantinterdependence between test generation at the register-transferand gate levels.For several benchmark circuits, we experimentally studied theperformance of the two-pass approach using a symbolic RTL testgenerator, TAO, and efficient gate-level test generators, HITECand SEST. Experimental results show that the proposed two-passapproach achieves a maximum speedup of 103X over a single-passgate-level sequential test generator. The average speedup was38X. No design for testability modifications were assumed for thecircuits.