Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Computer Architecture and Organization
Computer Architecture and Organization
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DFT guidance through RTL test justification and propagation analysis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
A controller redesign technique to enhance testability of controller-data path circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Hierarchical test approaches address the complexity of test generation through symbolic reachability paths that provide access to the I/Os of each module in a hierarchical design. While transparency behavior suitable for symbolic design traversal can be utilized for datapath modules, control modules do not exhibit transparency, and therefore require exhaustive search algorithms or expensive DFT hardware. In this paper, we introduce a fast hierarchical test path identification methodology for circuits with no DFT at the controller-datapath interface. We introduce the concept of Influence Tables, modeling the impact of control states on the datapath, based on which appropriate state sequences for accessing each module are identified. Imposition of such sequences on a hierarchical test path identification algorithm, in the form of constraints, results in significant speedup over alternative non-DFT based approaches.