False path exclusion in delay analysis of RTL-based datapath-controller designs

Predicting area-time tradeoffs for pipelined design

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference

Knowledge based control in micro-architecture design

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference

3D scheduling: high-level synthesis with floorplanning

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

Combined topological and functionality based delay estimation using a layout-driven approach for high level applications

EURO-DAC '92 Proceedings of the conference on European design automation

Timing models for high-level synthesis

EURO-DAC '92 Proceedings of the conference on European design automation

SYNTEST: an environment for system-level design for test

EURO-DAC '92 Proceedings of the conference on European design automation

A layout estimation algorithm for RTL datapaths

DAC '93 Proceedings of the 30th international Design Automation Conference

False loops through resource sharing

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Exploiting multi-cycle false paths in the performance optimization of sequential circuits

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference

Facet: A procedure for the automated synthesis of digital systems

DAC '83 Proceedings of the 20th Design Automation Conference

Datapath optimization using feedback

EURO-DAC '91 Proceedings of the conference on European design automation