Retargetable compilation for low power

Authors:
Wen-Tsong Shiue
Affiliations:
Silicon Metrics Corporation, 12710 Research Blvd. Suite 300, Austin, TX
Venue:
Proceedings of the ninth international symposium on Hardware/software codesign
Year:
2001

Citing 6
Cited 3

Bulldog: a compiler for VLSI architectures

Bulldog: a compiler for VLSI architectures
Efficient instruction scheduling for a pipelined architecture

SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Improvements to graph coloring register allocation

ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation and binding for low power

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power analysis and minimization techniques for embedded DSP software

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Fine-Grain Parallelizing Compiler

A Fine-Grain Parallelizing Compiler

References

SystemC
Automated empirical tuning of scientific codes for performance and power consumption

Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Proceedings of the 9th conference on Computing Frontiers

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Abstract

Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy consumption for architecture-aware compilation. In this paper, we focus on providing support for one architectural feature of DSPs that makes code generation difficult, namely the use of multiple data memory banks. This feature increases memory bandwidth by permitting multiple data memory accesses to occur in parallel when the referenced variables belong to different data memory banks and the registers involved conform to a strict set of conditions. We present novel instruction scheduling algorithms that attempt to maximize the performance, minimize the energy, and therefore, maximize the benefit of this architectural feature. Experimental results demonstrate that our algorithms generate high performance, low energy codes for the DPS architectural features with multiple data memory banks. Our algorithm led to improvements in performance and energy consumption of 48.3% and 66.6% respectively in our benchmark examples.