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Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
IEEE Transactions on Parallel and Distributed Systems
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 14th international symposium on Systems synthesis
Proceedings of the 15th international symposium on System Synthesis
Low power system scheduling and synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Communication speed selection for embedded systems with networked voltage-scalable processors
Proceedings of the tenth international symposium on Hardware/software codesign
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic adaptation for fault tolerance and power management in embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Proceedings of the 2004 international symposium on Low power electronics and design
Fast and efficient voltage scheduling by evolutionary slack distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal voltage allocation techniques for dynamically variable voltage processors
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coscheduling of processor voltage and control task period for energy-efficient control systems
ACM Transactions on Embedded Computing Systems (TECS)
HiPC'07 Proceedings of the 14th international conference on High performance computing
Sleep-aware mode assignment in wireless embedded systems
Journal of Parallel and Distributed Computing
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Efficient voltage scheduling and energy-aware co-synthesis for real-time embedded systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multiprocessor system in which the processors are capable of dynamically varying their core voltages, the optimum voltage levels for all the tasks in order to minimize the average power consumption under a given performance constraint. An effective local search approach for static voltage scaling based on the concept of a period graph has been demonstrated in [1]. To make use of it in an optimization problem, the period graph must be integrated into a global search algorithm. Simulated heating, a general optimization framework developed in [19], is an efficient method for precisely this purpose of integrating local search into global search algorithms. However, little is known about the management of computational (compile-time) resources between global search and local search in hybrid algorithms, such as those coordinated by simulated heating. In this paper, we explore various hybrid search management strategies for power optimization under the framework of simulated heating. We demonstrate that careful search management leads to significant power consumption improvement over add-hoc global search / local search integration, and explore alternative approaches to performing hybrid search management for dynamic voltage scaling.