Power-Aware scheduling for hard real-time embedded systems using voltage-scaling enabled architectures

Authors:
Amjad Mohsen;Richard Hofmann
Affiliations:
Department of Computer Science 7, University of Erlangen-Nürnberg, Erlangen, Germany;Department of Computer Science 7, University of Erlangen-Nürnberg, Erlangen, Germany
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

In this paper, we present a power-aware scheduling scheme for hard real-time embedded systems design. Our new approach can enhance the efficiency of both dynamic voltage scaling (DVS) and dynamic Vth scaling (DVTS). While optimizing the schedule in the time domain, the priorities of the tasks are modified dynamically based on their contribution to the overall power/energy reduction. The scheduling scheme leads to better “distribution” and “utilization” of slack intervals in the system which in return improves the efficiency of voltage scaling techniques. The voltage schedule is generated based on a global view of the components' energy profile when executing different tasks. The experimental results prove the applicability of our approach.