Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems

  • Authors:
  • Jiong Luo;Niraj K. Jha

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

This paper presents a power-aware real-timedistributed embedded system scheduling algorithm. It triesto satisfy the hard real-time constraints and precedence relationships of the tasks in the distributed embedded systemspecification. At the same time, it performs variable voltage scaling by addressing variations in power consumptionof different tasks and characteristics of different voltage-scalable processing elements (PEs) in an effective and efficient manner. It performs execution order optimization ofscheduled events to increase the chances of scaling downvoltages and frequencies of these voltage-scalable PEs inthe distributed embedded system. It also performs power-profile and timing-constraint driven slack allocation to maximize power reduction via voltage scaling. This schedulingalgorithm is also very effective in the case where the variations in power consumption of different tasks can be ignored.It can be included in the inner loop of a system-level synthesis tool for real-time heterogeneous embedded systemssince it is very fast. It is superior to other approaches inthe literature in terms of power consumption or complexity.