Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors

Authors:
Meikang Qiu;Zhong Ming;Jiayin Li;Shaobo Liu;Bin Wang;Zhonghai Lu
Affiliations:
Dept. of Elec. and Comp. Engr., University of Kentucky, Lexington, KY 40506, USA;College of Comp. Sci. and Software Engr., Shenzhen University, Shenzhen, GD 518060, China;Dept. of Elec. and Comp. Engr., University of Kentucky, Lexington, KY 40506, USA;Marvell Semiconductor, Marlborough, MA 01752, USA;Dept. of Comp. Sci. and Engr., Wright State University, Dayton, OH 45435, USA;Dept. of Electronic Systems, School for ICT, KTH Royal Institute of Technology, Sweden
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2012

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Abstract

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications' task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks' execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.