An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures

• Authors: Krishnan Srinivasan;Karam S. Chatha
• Venue: VLSID '04 Proceedings of the 17th International Conference on VLSI Design
• Year: 2004

System-level low power scheduling techniques are requiredfor optimizing th performance and power of embeddedapplications that are mapped to multiprocessorSystem-on-Chip (SoC) architectures.In this paper, wepresent an integer linear programming (ILP) formulationthat combines loop transformations (pipelining andunrolling) and system-level low power optimization techniques(dynamic voltage scaling (DVS) and power management(DPM)) to minimize the power consumption,while satisfying the period and deadline constraints ofthe application.We also present three modifications thatrelax one or more constraints in the optimal formulationin order to obtain smaller run times.We presentexperimental analysis by applying the formulations onan MPEG decoder algorithm.All results are comparedagainst two existing techniques.Our formulations resultin large system-level power reductions (max: 48.2%,min: 15.92%, avg: 31.9%).The modified ILP formulationsresult in exponential decrease in runtimes, and acorresponding linear degradation in the result quality.