Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Improving dynamic voltage scaling algorithms with PACE
Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Automatic performance setting for dynamic voltage scaling
Proceedings of the 7th annual international conference on Mobile computing and networking
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Saving energy with architectural and frequency adaptations for multimedia applications
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
What is the limit of energy saving by dynamic voltage scaling?
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A trace-based binary compilation framework for energy-aware computing
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Practical PACE for embedded systems
Proceedings of the 4th ACM international conference on Embedded software
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
ACM Transactions on Architecture and Code Optimization (TACO)
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Coordinated, distributed, formal energy management of chip multiprocessors
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Efficient behavior-driven runtime dynamic voltage scaling policies
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Phase-based visualization and analysis of Java programs
Science of Computer Programming - Special issue: Principles and practices of programming in Java (PPPJ 2004)
Collaborative operating system and compiler power management for real-time applications
ACM Transactions on Embedded Computing Systems (TECS)
Reducing NoC energy consumption through compiler-directed channel voltage scaling
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Power-aware scheduling for makespan and flow
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Trace-based leakage energy optimisations at link time
Journal of Systems Architecture: the EUROMICRO Journal
A unified practical approach to stochastic DVS scheduling
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Minimizing expected energy consumption in real-time systems through dynamic voltage scaling
ACM Transactions on Computer Systems (TOCS)
A comparison of automation techniques for optimization of compressor scheduling
Advances in Engineering Software
Bounding energy consumption in large-scale MPI programs
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Fine-grained energy profiling for power-aware application design
ACM SIGMETRICS Performance Evaluation Review
Methods for power optimization in SOC-based data flow systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-aware scheduling for makespan and flow
Journal of Scheduling
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
performance/energy optimization of dsp transforms on the XScale processor
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
The design and implementation of the DVS based dynamic compiler for power reduction
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Interval-based models for run-time DVFS orchestration in superscalar processors
Proceedings of the 7th ACM international conference on Computing frontiers
Fine-grained DVFS using on-chip regulators
ACM Transactions on Architecture and Code Optimization (TACO)
RAFT: A router architecture with frequency tuning for on-chip networks
Journal of Parallel and Distributed Computing
Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Compiler-Directed energy-aware prefetching optimization for embedded applications
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Energy-Constrained prefetching optimization in embedded applications
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
From the origins of performance evaluation to new green ICT performance engineering
PERFORM'10 Proceedings of the 2010 IFIP WG 6.3/7.3 international conference on Performance Evaluation of Computer and Communication Systems: milestones and future challenges
Exploring multi-threaded Java application performance on multicore hardware
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
Green streams for data-intensive software
Proceedings of the 2013 International Conference on Software Engineering
Energy-efficient work-stealing language runtimes
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
ACM Transactions on Embedded Computing Systems (TECS)
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With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-time power-management techniques, dynamic voltage scaling (DVS) has emerged as an important approach, with the ability to provide significant power savings. DVS exploits the ability to control the power consumption by varying a processor's supply voltage (V) and clock frequency (f). DVS controls energy by scheduling different parts of the computation to different (V, f) pairs; the goal is to minimize energy while meeting performance needs. Although processors like the Intel XScale and Transmeta Crusoe allow software DVS control, such control has thus far largely been used at the process/task level under operating system control. This is mainly because the energy and time overhead for switching DVS modes is considered too large and difficult to manage within a single program.In this paper we explore the opportunities and limits of compile-time DVS scheduling. We derive an analytical model for the maximum energy savings that can be obtained using DVS given a few known program and processor parameters. We use this model to determine scenarios where energy consumption benefits from compile-time DVS and those where there is no benefit. The model helps us extrapolate the benefits of compile-time DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through optimal settings of DVS modes. This is done by extending the existing Mixed-integer Linear Program (MILP) formulation for this problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical bounds for use into the future.