DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Advanced compiler design and implementation
Advanced compiler design and implementation
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Slack: maximizing performance under technological constraints
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Process cruise control: event-driven clock scaling for dynamic power management
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
An infrastructure for adaptive dynamic optimization
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Compile-time dynamic voltage scaling settings: opportunities and limits
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Positional adaptation of processors: application to energy reduction
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the conference on Design, automation and test in Europe - Volume 1
The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Impact of virtual execution environments on processor energy consumption and hardware adaptation
Proceedings of the 2nd international conference on Virtual execution environments
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
A dynamic binary instrumentation engine for the ARM architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
An intra-task dvfs technique based on statistical analysis of hardware events
Proceedings of the 4th international conference on Computing frontiers
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
PICSEL: measuring user-perceived performance to control dynamic frequency scaling
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Reducing pressure in bounded DBT code caches
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Designing a power efficiency framework for battery powered systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
Dynamic cache clustering for chip multiprocessors
Proceedings of the 23rd international conference on Supercomputing
Addressing the challenges of DBT for the ARM architecture
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Adapting application execution in CMPs using helper threads
Journal of Parallel and Distributed Computing
Dynamically utilizing computation accelerators for extensible processors in a software approach
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Computer Networks: The International Journal of Computer and Telecommunications Networking
Reducing exit stub memory consumption in code caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Proceedings of the 2010 ACM Symposium on Applied Computing
The design and implementation of the DVS based dynamic compiler for power reduction
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Interval-based models for run-time DVFS orchestration in superscalar processors
Proceedings of the 7th ACM international conference on Computing frontiers
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
A binary instrumentation tool for the Blackfin processor
Proceedings of the Workshop on Binary Instrumentation and Applications
Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications
Proceedings of the 37th annual international symposium on Computer architecture
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques
Journal of Systems Architecture: the EUROMICRO Journal
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Proceedings of the Conference on Design, Automation and Test in Europe
Using dynamic compilation for continuing execution under reduced memory availability
Proceedings of the Conference on Design, Automation and Test in Europe
Balancing memory and performance through selective flushing of software code caches
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Enhanced heterogeneous code cache management scheme for dynamic binary translation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
The alarms project: a hardware/software approach to addressing parameter variations
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fine-grained DVFS using on-chip regulators
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A dynamic power-aware partitioner with task migration for multicore embedded systems
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Memory access aware on-line voltage control for performance and energy optimization
Proceedings of the International Conference on Computer-Aided Design
Architecture support for disciplined approximate programming
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Extending a multicore multithread simulator to model power-aware hard real-time systems
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
SERA-IO: Integrating Energy Consciousness into Parallel I/O Middleware
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
Memory optimization of dynamic binary translators for embedded systems
ACM Transactions on Architecture and Code Optimization (TACO)
Exploring multi-threaded Java application performance on multicore hardware
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
StarDBT: an efficient multi-platform dynamic binary translation system
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Runtime performance projection model for dynamic power management
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Enabling dynamic binary translation in embedded systems with scratchpad memory
ACM Transactions on Embedded Computing Systems (TECS)
GPUWattch: enabling energy optimizations in GPGPUs
Proceedings of the 40th Annual International Symposium on Computer Architecture
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Architecture and Code Optimization (TACO)
Dynamic microarchitectural adaptation using machine learning
ACM Transactions on Architecture and Code Optimization (TACO)
Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling
Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization
Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization
StreaMorph: a case for synthesizing energy-efficient adaptive programs using high-level abstractions
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrialstrength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3X-5X better than static voltage scaling, and is more than 2X (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control.