Balancing memory and performance through selective flushing of software code caches

  • Authors:

  • Apala Guha;Kim Hazelwood;Mary Soffa

  • Affiliations:

  • University of Virginia, Charlottesville, Virginia, USA;University of Virginia, Charlottesville, Virginia, USA;University of Virginia, Charlottesville, Virginia, USA

  • Venue:
  • CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
  • Year:
  • 2010

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Abstract

Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all platforms, and especially embedded systems. The memory demand is typically controlled by placing a limit on cached translations and forcing the DBT to flush all translations upon reaching the limit. This solution manifests as a performance inefficiency because many flushed translations require retranslation. Ideally, translations should be selectively flushed to minimize retranslations for a given memory limit. However, three obstacles exist:(1) it is difficult to predict which selections will minimize retranslation,(2) selective flushing results in greater book-keeping overheads than full flushing, and(3) the emergence of multicore processors and multi-threaded programming complicates most flushing algorithms. These issues have led to the widespread adoption of full flushing as a standard protocol. In this paper, we present a partial flushing approach aimed at reducing retranslation overhead and improving overall performance, given a fixed memory budget. Our technique applies uniformly to single-threaded and multi-threaded guest applications