Performance analysis and predictability of the software layer in dynamic binary translators/optimizers

  • Authors:

  • Aleksandar Branković;Kyriakos Stavrou;Enric Gibert;Antonio González

  • Affiliations:

  • Universitat Politècnica de Catalunya, Spain;Intel Barcelona Research Center, Intel Labs Barcelona, Spain;Intel Barcelona Research Center, Intel Labs Barcelona, Spain;Intel Barcelona Research Center, Intel Labs Barcelona, Spain

  • Venue:
  • Proceedings of the ACM International Conference on Computing Frontiers
  • Year:
  • 2013

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Abstract

Dynamic Binary Translators and Optimizers (DBTOs) have been established as a common architecture during the last years. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed microarchitectures. Although many researchers worked on characterizing and reducing the emulation overhead, there are no published results that explain how the DBTO behaves from the microarchitectural prospective and how its behavior may be predicted based on high-level, guest application statistics. Such results are important for guiding design decisions and system optimization. In this paper we study the DBTO as an independent application by dividing its functionality into modules. We show that the behavior of the DBTO is not constant at all. The contribution of the different modules in the total overhead, the overhead itself, the microarchitectural interaction with the emulated application and the microarchitectural profile of the different modules changes significantly based on the emulated application. This result comes in contrast to numerous papers that consider this behavior constant and exclude the DBTO from the simulation. Throughout this paper we detail this variance, we quantify it and we explain the reasons behind it. The insights presented in this work can be exploited towards the design of more efficient DBTOs and their early performance evaluation.