Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Run-time power control scheme using software feedback loop for low-power real-time application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Low-energy intra-task voltage scheduling using static timing analysis
Proceedings of the 38th annual Design Automation Conference
Process cruise control: event-driven clock scaling for dynamic power management
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor
Proceedings of the conference on Design, automation and test in Europe
Compiler-directed dynamic voltage and frequency scaling for cpu power and energy reduction
Compiler-directed dynamic voltage and frequency scaling for cpu power and energy reduction
lmbench: portable tools for performance analysis
ATEC '96 Proceedings of the 1996 annual conference on USENIX Annual Technical Conference
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Dynamic voltage and frequency scaling based on workload decomposition
Proceedings of the 2004 international symposium on Low power electronics and design
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Hierarchical power management with application to scheduling
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An intra-task dvfs technique based on statistical analysis of hardware events
Proceedings of the 4th international conference on Computing frontiers
TSB: A DVS algorithm with quick response for general purpose operating systems
Journal of Systems Architecture: the EUROMICRO Journal
Enhanced reliability-aware power management through shared recovery technique
Proceedings of the 2009 International Conference on Computer-Aided Design
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
On improving performance and energy profiles of sparse scientific applications
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Conjugate gradient sparse solvers: performance-power characteristics
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
An analytical model for predicting the remaining battery capacity of lithium-ion batteries
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power techniques for an android based phone
ACM SIGARCH Computer Architecture News
Generalized reliability-oriented energy management for real-time embedded applications
Proceedings of the 48th Design Automation Conference
Journal of Systems and Software
Effective dynamic voltage scaling through CPU-Boundedness detection
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Power agnostic technique for efficient temperature estimation of multicore embedded systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Predicting Performance Impact of DVFS for Realistic Memory Systems
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
E3: energy-efficient engine for frame rate adaptation on smartphones
Proceedings of the 11th ACM Conference on Embedded Networked Sensor Systems
UCC '13 Proceedings of the 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing
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This paper presents an intra-process dynamic voltage and frequency scaling (DVFS) technique targeted toward non real-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically-constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot, and thus, adjust its voltage and frequency in order to save energy while meeting soft timing constraints. This is in turn achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15-60% CPU energy saving was achieved at the cost of 5-20% performance penalty.