Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Communication speed selection for embedded systems with networked voltage-scalable processors
Proceedings of the tenth international symposium on Hardware/software codesign
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems
Proceedings of the 2004 international symposium on Low power electronics and design
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
The Journal of Supercomputing
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Journal of Signal Processing Systems
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Dynamic voltage scaling has been widely acknowledged as a powerful technique for trading off power consumption and delay for processors. Recently, variable-frequency (and variable-voltage) parallel and serial links have also been proposed, which can save link power consumption by exploiting variations in bandwidth requirement. In this paper, we address joint dynamic voltage scaling for variable-voltage processors and communication links in such systems. We propose a scheduling algorithm for real-time applications, with both data flow and control flow information captured. It performs efficient routing of communication events through multi-hops, as well as efficient slack allocation among heterogeneous processors and communication links to maximize energy savings, while meeting all real-time constraints.