An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
Proceedings of the ninth international symposium on Hardware/software codesign
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Minimizing Energy Consumption for High-Performance Processing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating communication protocol selection with hardware/software codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 15th international symposium on System Synthesis
Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems
Proceedings of the 2004 international symposium on Low power electronics and design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Synchronization-driven dynamic speed scaling for MPSoCs
Proceedings of the 2006 international symposium on Low power electronics and design
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Energy Saving Approach through Mobile Collaborative Computing Systems
International Journal of Handheld Computing Research
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High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We formulate a multi-dimensional optimization problem by modeling communication dependencies between processors and their timing budgets. This enables engineers to systematically solve the problem of optimal speed selection for global energy reduction. We demonstrate the effectiveness of our speed selection approach with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.