Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

  • Authors:

  • Hongzhong Zheng;Jiang Lin;Zhao Zhang;Eugene Gorbatov;Howard David;Zhichun Zhu

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA;Department of Electrical and Computer Engineering, Iowa State University, USA;Department of Electrical and Computer Engineering, Iowa State University, USA;Corporate Technology Group, Intel Corp., Hillsboro, OR 9712, USA;Corporate Technology Group, Intel Corp., Hillsboro, OR 9712, USA;Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA

  • Venue:
  • Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2008

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Abstract

The widespread use of multicore processors has dramatically increased the demand on high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to meet the demand, memory power consumption is now approaching that of processors. However, the conventional DRAM architecture prevents any meaningful power and performance trade-offs for memory-intensive workloads. We propose a novel idea called mini-rank for DDRx (DDR/DDR2/DDR3) DRAMs, which uses a small bridge chip on each DRAM DIMM to break a conventional DRAM rank into multiple smaller mini-ranks so as to reduce the number of devices involved in a single memory access. The design dramatically reduces the memory power consumption with only a slight increase on the memory idle latency. It does not change the DDRx bus protocol and its configuration can be adapted for the best performance-power trade-offs. Our experimental results using four-core multiprogramming workloads show that using x32 mini-ranks reduces memory power by 27.0% with 2.8% performance penalty and using x16 mini-ranks reduces memory power by 44.1% with 7.4% performance penalty on average for memory-intensive workloads, respectively.