Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Automatic data migration for reducing energy consumption in multi-bank memory systems
Proceedings of the 39th annual Design Automation Conference
Scheduler-based DRAM energy management
Proceedings of the 39th annual Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
ACM Transactions on Embedded Computing Systems (TECS)
When physical is not real enough
Proceedings of the 11th workshop on ACM SIGOPS European workshop
Design and implementation of power-aware virtual memory
ATEC '03 Proceedings of the annual conference on USENIX Annual Technical Conference
Software–hardware cooperative power management for main memory
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
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Power management is an important part of handheld systems such as PDAs, smartphones, and other battery operated digital devices. A handheld system can transition the nodes of a DRAM to low power state to reduce energy consumption. We propose an efficient method for dynamic power management (DPM) of DRAM based on accessed physical addresses. The proposed method also reduces the number of times resynchronization is done. There is no need to collect scattered pages, as in conventional page clustering mechanisms that focus on virtual memory (VM). Simulation result shows that the proposed method reduces Energy*Delay Product by as much as 75% when compared to DRAMs with no DPM.