The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation
IEEE Transactions on Computers
Dynamic power management of DRAM using accessed physical addresses
Microprocessors & Microsystems
Page placement in hybrid memory systems
Proceedings of the international conference on Supercomputing
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This position paper argues that policies for physical memory management and for memory power mode control should be relocated to the system software of a programmable memory management controller (MMC). Similarly to the mapping of virtual to physical addresses done by an MMU of a processor, this controller offers another level of mapping from physical addresses to real addresses in a multi-bank multi-technology (DRAM, MRAM, FLASH) memory system. Furthermore, the programmable memory controller is responsible for the allocation and migration of memory according to power and performance demands.Our approach dissociates the aspects of memory protection and sharing from the aspect of energy-aware management of real memory. In this way, legacy operating systems do not have to be extended to reduce memory power dissipation, and power-aware memory is no longer limited to CPUs with an MMU.