XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Proceedings of the 50th Annual Design Automation Conference
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SoC designers typically use a processor simulator to generate a memory trace and apply the generated trace to a memory simulator in order to collect the performance statistics of a complete system. This is an inaccurate process for most applications, making it difficult to optimize the processor and memory configurations. In this paper, we study the problems encountered in the typical simulation approach and propose a methodology which utilizes an interface layer component to link the processor simulator and memory simulator seamlessly. The interface layer component presented in this paper can be used as the connector between the processor module and memory module in building an execution-driven approach which can be applied to process run-time memory requests rather than the traditional trace driven simulation approaches. By applying the proposed interface layer component to link the processor simulator and memory simulator, the estimated performance statistics of the system and the average power consumption of the memory system can be collected with high accuracy. We prove the necessity of our approach by evaluating six benchmarks. Over these benchmarks, there is an 80% variation in the choice of memory latency to achieve the most accurate power consumption and a 16% variation in the choice of memory latency to achieve the most accurate execution time. The increase in accuracy comes at an average increase in simulation time of 13.5%.