Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Compiling Fortran D for MIMD distributed-memory machines
Communications of the ACM
Partitioning the statement per iteration space using non-singular matrices
ICS '93 Proceedings of the 7th international conference on Supercomputing
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
A Framework for Designing Deadlock-Free Wormhole Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
Global communication analysis and optimization
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Wormhole routing techniques for directly connected multicomputer systems
ACM Computing Surveys (CSUR)
Transient fault detection via simultaneous multithreading
Proceedings of the 27th annual international symposium on Computer architecture
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
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An adaptive low-power transmission scheme for on-chip networks
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IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing
IEEE Transactions on Parallel and Distributed Systems
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Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
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Power-aware communication optimization for networks-on-chips with voltage scalable links
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Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-level power analysis for on-chip networks
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ICCD '04 Proceedings of the IEEE International Conference on Computer Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing NoC energy consumption through compiler-directed channel voltage scaling
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High-level power analysis for multi-core chips
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Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
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Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Compiler-directed application mapping for NoC based chip multiprocessors
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SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
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ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
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Increasing complexity in the communication patterns of embedded applications parallelized over multiple processing units makes it difficult to continue using the traditional bus-based on-chip communication techniques. The main contribution of this paper is to demonstrate the importance of compiler technology in reducing power consumption of applications designed for emerging multi processor, NoC (Network-on-Chip) based embedded systems. Specifically, we propose and evaluate a compiler-directed approach to NoC power management in the context of array-intensive applications, used frequently in embedded image/video processing. The unique characteristic of the compiler-based approach proposed in this paper is that it increases the idle periods of communication channels by reusing the same set of channels for as many communication messages as possible. The unused channels in this case take better advantage of the underlying power saving mechanism employed by the network architecture. However, this channel reuse optimization should be applied with care as it can hurt performance if two or more simultaneous communications are mapped onto the same set of channels. Therefore, the problem addressed in this paper is one of reducing the number of channels used to implement a set of communications without increasing the communication latency significantly. To test the effectiveness of our approach, we implemented it within an optimizing compiler and performed experiments using twelve application codes and a network simulation environment. Our experiments show that the proposed compiler-based approach is very successful in practice and works well under both hardware based and software based channel turn-off schemes.