Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Authors:
Jieming Yin;Pingqiang Zhou;Anup Holey;Sachin S. Sapatnekar;Antonia Zhai
Affiliations:
University of Minnesota, Twin Cities, Minneapolis, MN, USA;University of Minnesota, Twin Cities, Minneapolis, MN, USA;University of Minnesota, Twin Cities, Minneapolis, MN, USA;University of Minnesota, Twin Cities, Minneapolis, MN, USA;University of Minnesota, Twin Cities, Minneapolis, MN, USA
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

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Abstract

Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.