Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Pipeline stage unification: a low-energy consumption technique for future mobile processors
Proceedings of the 2003 international symposium on Low power electronics and design
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NoC frequency scaling with flexible-pipeline routers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A single-cycle output buffered router with layered switching for Networks-on-Chips
Computers and Electrical Engineering
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.