On heterogeneous network-on-chip design based on constraint programming

Authors:
Ayhan Demiriz;Nader Bagherzadeh
Affiliations:
Sakarya University, Sakarya, Turkey;University of California Irvine, Irvine, CA
Venue:
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Year:
2013

Citing 10
Cited 0

Design and management of voltage-frequency island partitioned networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing the abstraction and optimality gaps in the allocation and scheduling for variable voltage/frequency MPSoC platforms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A NoC Traffic Suite Based on Real Applications

ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Optimal methods for resource allocation and scheduling: a cross-disciplinary survey

Constraints
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
MultiAmdahl: How Should I Divide My Heterogenous Chip?

IEEE Computer Architecture Letters
A heterogeneous multiple network-on-chip design: an application-aware approach

Proceedings of the 50th Annual Design Automation Conference
CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture

PDP '13 Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Core mapping and application scheduling problems coupled with routing schemes are essential design considerations for an efficient Network-on-Chip (NoC) design. This paper discusses heterogeneous NoC design from a Constraint Programming (CP) perspective using a two-stage solution. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage in order to minimize the overall communication cost among cores. We then solve the application scheduling problem in the second stage to determine the optimum core types from a list of technological alternatives and to minimize the makespan i.e. time to complete all tasks. As a design extension, surface area constraint can be introduced to the underlying problem. The paper reports results based on real benchmark datasets from the literature.