Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Automatic computation and data decomposition for multiprocessors
Automatic computation and data decomposition for multiprocessors
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
International Journal of Embedded and Real-Time Communication Systems
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The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multi-processor architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. Our experimental result clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.