Proceedings of the 27th annual international symposium on Computer architecture
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Adaptive History-Based Memory Schedulers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A power and temperature aware DRAM architecture
Proceedings of the 45th annual Design Automation Conference
Energy simulation of embedded XScale systems with XEEMU
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
The virtual write queue: coordinating DRAM and last-level cache policies
Proceedings of the 37th annual international symposium on Computer architecture
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
DRAM energy reduction by prefetching-based memory traffic clustering
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
DRAMSim2: A Cycle Accurate Memory System Simulator
IEEE Computer Architecture Letters
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Modern DRAMs provide multiple low-power states to save their energy consumption during idle times. The use of low-power states, however, can cause performance degradation because state transitions from low-power states to an active state incur time penalty. To effectively utilize the low-power states, we propose DRAM power-aware rank scheduling schemes applied to the last-level cache and the memory controller. Our scheme utilizing the last-level cache reduces write requests to DRAM and the state transitions by replacing cache blocks based on their dirty states and DRAM rank power states. Our scheme utilizing the memory controller decreases the state transitions with rank power state-aware batch writes. With the second scheme, the states transitions are reduced by 21.2%, on average. Consequently DRAM energy consumption is reduced by 11.2%, on average, with no performance loss.