Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Critical power slope: understanding the runtime effects of frequency scaling
ICS '02 Proceedings of the 16th international conference on Supercomputing
Embedded Software for Soc
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Dynamic voltage frequency scaling for multi-tasking systems using online learning
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
The synergy between power-aware memory systems and processor voltage scaling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
XEEMU: an improved xscale power simulator
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Energy-aware system design with SDL
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
SimTag: exploiting tag bits similarity to improve the reliability of the data caches
Proceedings of the Conference on Design, Automation and Test in Europe
DRAM energy reduction by prefetching-based memory traffic clustering
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Journal of Systems and Software
DRAM power-aware rank scheduling
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A fast and accurate methodology for power estimation and reduction of programmable architectures
Proceedings of the Conference on Design, Automation and Test in Europe
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Energy efficiency is key in embedded system design. Understanding the complex issue of software power consumption in early design phases is of extreme importance to make the right design decisions. Here, not only the CPU but also the external memory plays a very important role. Power simulators offer flexibility and allow a detailed view on the sources of power consumption. However, many simulators lack accuracy and focus only on the CPU core without considering the memory subsystem. In this paper, we present XEEMU, a fast, cycle-accurate simulator, which aims at accurately simulating the power consumption of an XScale-based system including its memory subsystem. It has been validated using measurements on real hardware and shows a high accuracy for runtime, instantaneous power, and total energy consumption estimation. The average error is as low as 3.0% and 1.6% for runtime and CPU energy consumption estimation, respectively.