A fast and accurate methodology for power estimation and reduction of programmable architectures

Authors:
Erwan Piriou;Raphaël David;Fahim Rahim;Solaiman Rahim
Affiliations:
CEA, LIST, Embedded Computing Lab, France;CEA, LIST, Embedded Computing Lab, France;Atrenta - Minatec Office, Grenoble France;Atrenta - Minatec Office, Grenoble France
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor.