IBM Journal of Research and Development
Proceedings of the 49th Annual Design Automation Conference
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
RAMZzz: rank-aware dram power management with dynamic migrations and demotions
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 14.98 |
DRAM memory is playing an increasingly important role in the overall power profile of latest-generation servers with multicore processors. With many power saving techniques adopted into processor design, memory power consumption can now exceed processor power consumption when a system runs memory-intensive workloads. There is an urgent need to fully evaluate the memory power profile of contemporary DRAM memories and to re-investigate DRAM memory designs, configurations, and optimizations from both power and performance perspectives. This study fills the gap by studying the performance and power consumption of multicore systems with DDR3 memory under different configurations. It includes comprehensive results regarding memory power breakdown, including background, operation, read/write, and I/O power, as well as performance. Comparisons with DDR2 and FB-DIMM are also included. The results show clearly that DRAM system configurations, including page policy, power mode, device configuration, burst length, channel organization, and the selection of DRAM technology, affects the memory power consumption significantly besides the performance. The optimal choice of some configurations is application-dependent, suggesting that reconfigurable or hybrid configurations are worth further studies.