Estimating influence of data layout optimizations on SDRAM energy consumption
Proceedings of the 2003 international symposium on Low power electronics and design
A Novel Implementation of Tile-Based Address Mapping
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Entry control in network-on-chip for memory power reduction
Proceedings of the 13th international symposium on Low power electronics and design
Reconfigurable microarchitecture based system-level dynamic power management soc platform
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
| Hi-index | 0.00 |
To improve memory bandwidth and power consumption in video applications, a new memory-interface architecture is proposed. The architecture adopts an array address-translation technique to utilize the fact that video processing algorithms have regular memory-access patterns. Since the translation can minimize the number of overhead cycles needed for row-activations in synchronous DRAM (SDRAM), we can improve the memory bandwidth and energy consumption significantly. The features of SDRAM and memory-access patterns of video processing applications are considered to find a suitable address translation. Compared to the conventional linear translation, experimental results show that the proposed architecture reduces about 89% of row-activations and increases the memory bandwidth by 50%. In addition, the proposed architecture reduces the energy consumption by 30% on the average