Reconfigurable microarchitecture based system-level dynamic power management soc platform

Authors:
Cheong-Ghil Kim;Dae-Young Jeong;Byung-Gil Kim;Shin-Dug Kim
Affiliations:
Supercomputing Lab, Dept. of Computer Science, Yonsei University, Seoul, Korea;Supercomputing Lab, Dept. of Computer Science, Yonsei University, Seoul, Korea;Supercomputing Lab, Dept. of Computer Science, Yonsei University, Seoul, Korea;Supercomputing Lab, Dept. of Computer Science, Yonsei University, Seoul, Korea
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power caused by data transfers over the conventional method in MC module.