Fabrication Technologies for Three-Dimensional Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
System power management support in the IBM POWER6 microprocessor
IBM Journal of Research and Development
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermal Management for 3D Processors via Task Scheduling
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Processor Architecture Design Using 3D Integration Technology
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Co-design of signal, power, and thermal distribution networks for 3D ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Design, CAD and technology challenges for future processors: 3D perspectives
Proceedings of the 48th Design Automation Conference
3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Proceedings of the International Conference on Computer-Aided Design
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited. Elevated stack temperatures have significant effect on the overall energy efficiency and reliability of the processor; they also limit the potential peak performance improvement from the 3D implementation. Thermal characteristics of 3D stacks differ from 2D processors in various ways including: the nature of heat dissipation throughout the stack, thermal conductivity of the 3D structures such as micro-C4 layers, and hotspot interactions among layers. The intensity of the corresponding thermal problems is highly dependent on the 3D technology, processor and stack parameters. In this study we focus on spatial and temporal thermal characteristics of 3D multicore architectures using high-fidelity technology and processor models. Our experimental results highlight the need for integrating detailed thermal models in the design flow, starting with the early design stages. In addition, the reduced time constants and elevated on-chip temperatures indicate faster response time requirements for dynamic thermal management in processor stacking options.