Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Challenges in verifying an integrated 3D design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level innovation, which provided performance improvement in each processor generation. However, future processor designs face a number of key challenges in sustaining the growth trends. The dawn of the 22nm node, and beyond, marks an era of new trends and challenges; where the cost and complexity associated with each technology node is increasing at much faster rate than the device performance gains. Novel tools and design methodologies are needed to not only compensate for these challenges but also to leverage emerging technologies to achieve the desired performance in future processor architectures. Technology alternatives such as 3D integration have attracted significant interest as an additional way of sustaining the density scaling and performance growth. 3D integration provides some unique benefits for processor design, such as packaging density, interconnect bandwidth and latency, modularity, and heterogeneity. Packaging density improvement provided by 3D can be used to continue improvements in processing and storage capacity as well as enabling a gradual shift towards integrating the full system in one stack. Through-Silicon-Vias (TSVs) provide lower latency and higher bandwidth that improves interconnect-limited performance. 3D enables modular design of a variety of systems from a shared set of sub-components through functional separation of the device layers. As a result, different layers can be independently manufactured in the most cost effective ways, which can be stacked to compose a wide range of customized systems. Optimizing layer interfaces and infrastructure components, such as power delivery and clocking, can further enhance the inherent modularity advantages. 3D provides opportunities for composing future systems by integrating disparate technologies as well as different technology generations in the same stack. It can be used to incorporate a wide range of device layers including non-volatile memory layers, MEMS, FPGAs, DRAM or photonics in the same stack, easing the IO/off-chip bandwidth limitations. This provides the opportunity to enable processor architectures with new computation, storage and communication capabilities. The system-level benefits of 3D will be determined, to a significant degree, by the effectiveness of novel design methodologies that explore the new design space introduced by the vertical dimension. Design flow optimization is essential in achieving the highest performance gains as well as tackling the more prominent interdependencies among performance, power dissipation, temperatures, interconnectivity and reliability in 3D. This presentation will highlight these challenges and opportunities.