Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
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Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results. Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution networks, chip/package power supply noise analysis, wire congestion, chip layout imaging, and static circuit tuning. The goals, successes, and failures of these examples will be discussed, along with some unexpected benefits from our ability to easily see patterns in complex visualizations.