A Clock Methodology for High-Performance Microprocessors

  • Authors:

  • Keith M. Carrig;Albert M. Chu;Frank D. Ferraiolo;John G. Petrovick;P. Andrew Scott;Richard J. Weiss

  • Affiliations:

  • IBM Microelectronics Division, Essex Junction, Vermont;IBM Microelectronics Division, Essex Junction, Vermont;IBM Microelectronics Division, Essex Junction, Vermont;IBM Microelectronics Division, Essex Junction, Vermont;Cadence Design Systems, San Jose, California;First PASS, NW Palm Bay, Florida

  • Venue:
  • Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
  • Year:
  • 1997

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Abstract

This paper discusses an effective clock methodology for the design ofhigh-performance microprocessors. Key attributes include theclustering and balancing of clock loads, multiple clock domains, abalanced clock router with variable width wires to minimize skew,hierarchical clock wiring, automated verification, an interface tothe Cadence Design Framework II™ environment, and acomplete network model of the clock distribution, includingloads. This clock methodology enabled creation of the entire clocknetwork, including verification, in less than three days withapproximately 180 ps of skew.