A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
On implementing addition in VLSI technology
Journal of Parallel and Distributed Computing
Area-Time Optimal Adder Design
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
On the Average Number of Maxima in a Set of Vectors and Applications
Journal of the ACM (JACM)
Art and Theory of Dynamic Programming
Art and Theory of Dynamic Programming
Area-time efficient addition in charge based technology
DAC '81 Proceedings of the 18th Design Automation Conference
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
Constructive threshold logic addition: a synopsis of the last decade
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
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The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.