Area-time efficient addition in charge based technology

Authors:
Robert K. Montoye
Affiliations:
-
Venue:
DAC '81 Proceedings of the 18th Design Automation Conference
Year:
1981

Citing 2
Cited 2

On the Time Required to Perform Addition

Journal of the ACM (JACM)
Introduction to VLSI Systems

Introduction to VLSI Systems

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming

IEEE Transactions on Computers - Special issue on computer arithmetic
Constructive threshold logic addition: a synopsis of the last decade

ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing

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Abstract

Using the model developed by Mead and Conway for charge based technology, a methodology for the production of area-time efficient adders which imbeds the buffering required to drive large loads caused by the carry-lookahead tree has been developed. This methodology can be used to produce an O(logN) time and O(NlogN) area layout. Additionally, an algorithm was written to produce minimal silicon area layouts for a given time bound. This algorithm involves optimization at both the cellular level and the layout level in an iterative fashion to allow the relevant technological parameters to play a role in the cellular design phase. Results of the algorithm including examples and an area-time curve for a 48 bit adder using typical 5 micron NMOS [MeCo80] are displayed.