Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Variants of an Improved Carry Look-Ahead Adder
IEEE Transactions on Computers
Area-Time Optimal Adder Design
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Digit-Serial Complex-Number Multipliers on FPGAs
Journal of VLSI Signal Processing Systems
Performance enhancement for variable block optimization in FGPA synthesis process
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Synthesis optimization by redesigning FPGA architecture for area-speed optimization
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
| Hi-index | 0.00 |
The delay models and costs analysis developed for ASIC technology are not useful for the design and implementation of fixed-point adders on FPGA devices. This paper discusses the implementation of fixed-point adders on the Xilinx 4k series devices and studies their related costs and operational delays. This work also proposes the timing models for the optimization analyses of the carry-skip and the carry-select adders and their optimization schemes. The comparison of the performances and costs of different fixed-point FPGA adders will be a useful source of information for the FPGA-based computing systems designers. The study should contribute to effective and cost-efficient designs of computational units on FPGA devices.