On implementing addition in VLSI technology
Journal of Parallel and Distributed Computing
Revisiting the cascade circuit in logic cells of lookup table based FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
Optimizations for a simulator construction system supporting reusable components
Proceedings of the 40th annual Design Automation Conference
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
IEEE Transactions on Nanotechnology
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In FPGAs the data path computations are all optimized for delay and logical depth. Still current FPGAs support modification in the existing internal scheme to provide higher performance computations. This paper presents how an optimization can be achieved by redesigning the FPGA architecture of carry propagation stage. The data computation path is modified with two different structures to reduce the delay aspect and the number of logic levels. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.