Computer
Regular, area-time efficient carry-lookahead adders
Journal of Parallel and Distributed Computing
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Journal of the ACM (JACM)
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A Collection of Papers on Magic
A Collection of Papers on Magic
Circuit Design Techniques for a Floating-Point Processor
Circuit Design Techniques for a Floating-Point Processor
IEEE Transactions on Computers - Special issue on computer arithmetic
ELM-A Fast Addition Algorithm Discovered by a Program
IEEE Transactions on Computers
Evaluation of A+B=K Conditions Without Carry Propagation
IEEE Transactions on Computers
A performance driven generator for efficient testable conditional-sum-adders
EURO-DAC '92 Proceedings of the conference on European design automation
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Comments on "Area-Time Optimal Adder Design"
IEEE Transactions on Computers
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Constructive threshold logic addition: a synopsis of the last decade
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
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A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS.