Area-Time Optimal Adder Design
IEEE Transactions on Computers
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This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit. Three most interesting circuit blocks are discussed which include a fast adder, a leading one detector and a shifter. Mixed logic with static and dynamic circuits are used. The chip is implemented in a 1.6 micron, N-well, double-metal CMOS process (HP CMO5-10). The timing and area of the above three modules are as follows: 66 bit adder *Delay--Crystal 36 ns, SPICE 33 ns *Size--4757x553 Lambda, which is 3806 x 442um 67 bit Leading one detector *Delay--Crystal 20.8 ns, SPICE 18 ns *Size--4901 x 463 lambda, which is 3920 x 320 um 67 bit shifter with Sticky Logic *Delay--Shifting 15 ns, Sticky bit (latched mic output latch) 25 ns *Size--The whole module with decoder is 5359 x 1414 lambda, which is 4287 x 1131 um. c C