Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Iterative construction of binary lookahead addition trees
Computers and Electrical Engineering
An overview of the Penn State design system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Area-Time Optimal Adder Design
IEEE Transactions on Computers
On the Time Required to Perform Addition
Journal of the ACM (JACM)
On the Time Required to Perform Multiplication
Journal of the ACM (JACM)
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Unifying carry-sum and signed-digital number representations for low power
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Delay efficient 32-bit carry-skip adder
VLSI Design
Constructive threshold logic addition: a synopsis of the last decade
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
International Journal of Critical Computer-Based Systems
Power-delay characteristics of CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
A new addition algorithm, ELM, is presented. This algorithm makes use of a tree of simple processors and requires O(log n) time, where n is the number of bits in the augend and addend. The sum itself is computed in one pass through the tree. This algorithm was discovered by a VLSI CAD tool, FACTOR, developed for use in synthesizing CMOS VLSI circuits.