Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
ELM-A Fast Addition Algorithm Discovered by a Program
IEEE Transactions on Computers
Fault-tolerant computer system design
Fault-tolerant computer system design
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Self-Dual Modules in Design of Dependable Digital Devices
DEPCOS-RELCOMEX '06 Proceedings of the International Conference on Dependability of Computer Systems
Design of a fault-tolerant conditional sum adder
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Analysis and Evaluation of a New Algorithm Based Fault Tolerance for Computing Systems
International Journal of Grid and High Performance Computing
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Several measures can be undertaken to achieve fault-tolerance of arithmetic devices. They differ in the level of hardware redundancy and the coverage of detectable faults. The discussion of the possible solutions for fast fault tolerant adders is given in the paper. The hardware complexity growth and latency overhead of various designs with respect to fault-coverage is discussed in the paper. It is shown that the designs of fast fault-tolerant adders based on the concept of residue code or double-rail code are preferable.